Jinwoo Suh, Ph. D. (서진우 in Korean)

Tel: Office: 703-248-6160

Email: jsuh@isi_.edu (please remove “_” after isi.)

Education

- Ph.D., Electrical Engineering-Systems, August, 1999

University of Southern California (USC), Los Angeles, CA

Dissertation: "Efficient Communication Algorithms for Parallel Computing Platforms"

Advisor: Dr. Viktor K. Prasanna

- MS, Electrical Engineering, February, 1990

Korea Advanced Institute of Science and Technology (KAIST), Seoul, Korea

Thesis: "An Efficient Line Detection Algorithm using A* Algorithm"

Advisor: Dr. Seongdae Kim

- BS, Electronic and Electrical Engineering, February, 1988

Dongguk University, Seoul, Korea

Honors and Awards

- Merit Award (06): USC/ISI, Arlington, VA, USA

- Scholarship (94-99): DAEWOO Electronics Co., Ltd., Seoul, Korea

- Scholarship (88-90): KAIST, Seoul, Korea

- Scholarship (84-88): Dongguk University, Seoul, Korea

- Scholarship (81-84): Kyunggi Provincial Government, Kyunggi, Korea

- Scholarship (81): Congressman Jung's Scholarship, Korea

- Scholarship (80): Congressman Park's Scholarship, Korea

Professional Activities

- Computer Scientist, USC/Information Sciences Institute (USC/ISI), 1999 – Present

- Seminars at KAIST, Daejeon, Korea , and GIST, Kwangjoo, Korea, 2007

- Program Committee, HiPC, 2003

- Program Committee, Embedded High Performance Computing, 2001

- Reviewer, Ad hoc journals and conferences

- Research Assistant, Electrical Engineering, USC, 1996 - 1999

- Member of IEEE, 2000 - Present

- Student member of IEEE, 1997 - 1999

- Teacher, Training for international engineers invited by Korea Government, 1994

Research Experience

- Computer Scientist: USC/ISI (1999-Present)

• SLANG (Signal processing LANGuage), a domain-specific language, development
• Research on design pattern for defense applications
• Domain-specific processor architecture design tool development
• Mapping of signal processing applications for tiled-architecture processor Tile64 processor developed by Tilera.
• Implementation of MPI library for tiled-architecture processor Tile64 processor.
• FPU design and a simulator development for a processor for space use based on Tile64 processor.
• Mapping of signal processing applications and benchmarks such as FIR filter bank for MONARCH MONARCH processor developed by Raytheon and ISI.
• Mapping of signal processing applications and benchmarks such as Ground Moving Target Indicator (GMTI) for MIT Raw processor boards developed by ISI in conjunction with MIT. The mapping was performed in the framework of Stream Virtual Machine (SVM) developed by reserach community supported morphware forum. An SVM library on Raw was developed and performance was analyzed and tuned to access the Raw architecture and proposed SVM.
• Mapping of data intensive applications such as corner turn, coherent sidelobe canceller, and beam forming for the System-Level Intelligence Intensive Computing (SLIIC) boards that use Commercial-Off-The-Shelf (COTS) processors, V-IRAM (a processor-in memory vector processor being developed by University of California at Berkeley), and Imagine (a stream processor being developed by Stanford University).
• Developed a SLIIC architecture for the system and software for the processors and firmware for the interconnection network that connects multiple processor-in-memory(PIM) using VHSIC Hardware Description Language (VHDL).
• Developing a Power-Aware Multiprocessor Architecture (PAMA). Developing architecture that intelligently controls the power usage and performance to maximize operating time and performance. Developing Application Programming Interface (API) and applications for the PAMA system.

- Research Assistant (1996-1999): EE-Systems, USC

• Developed parallel communication algorithms for throughput-oriented architecture under a project supported by Rome Lab. Implemented Signal processing applications such as Matrix Transpose and Synthetic Aperture Radar on high-performance computing platforms.
• Developed parallel disk I/O algorithms under a project supported the US Army Corps of Engineers Waterways Experiment Station (CEWES). Developed a model of high-performance computing Systems and parallel disk I/O algorithms and parallel communication algorithms.

- Research Engineer (1990-1994): DAEWOO Electronics Co., Ltd, Seoul, Korea

• Developed High-Definition TV (HDTV) and D/D2-MAC Decoder.

- Research Assistant (1989-1991): Image Processing Lab., EE, KAIST, Seoul, Korea

• Developed a line detection algorithm and map database system under a project supported by Agency for Defense Development, a research center managed by Korea government.

Publications

• M. Kang, E. Park, M. Cho, J. Suh, D.-I. Kang, and S. P. Crago “MPI Performance Analysis and Optimization on Tile64/Maestro,” Workshop on Multi-core Processors for Space – Opportunities and Challenges held in conjunction with SMC-IT, Pasadena, CA, July 2009.
• M. Kang, D.-I. Kang, J. Suh, “Real-Time support on IEEE 802.11 Wireless Ad-Hoc Networks Reality vs. Theory,” IEICE Trans. On Communications, Vol. E92-B, No. 3, pp. 737-744, March 2009.
• M. Kang, D.-I. Kang, J. Suh, and J. Lee, “An energy-efficient real-time scheduling scheme on dual-channel networks,” Information Sciences, Vol. 178, pp. 2553-2563, June 2008.
• M. Kang, D.-I. Kang, J. Suh, and J. Lee, “A Low Power Real-Time Packet Scheduling Scheme on Wirelss Local Area Networks,” IEICE Trans. on Communications, Vol. E90-B, No. 12, pp. 3501-3504, December 2007.
• J. Suh, J. O. McMahon, S. P. Crago, and D.-I. Kang, “Optimization of Memory Allocation in VSIPL,” High Performance Embedded Computing (HPEC), Lexington, MA, September 2007.
• D. Kang, J. Suh, J. O. McMahon, and S. P. Crago, “Preliminary Study toward Intelligent Run-time Resource Management Techniques for Large Multi-Core Architectures,” High Performance Embedded Computing (HPEC), Lexington, MA, September 2007.
• D.-I. Kang, S. P. Crago, J. Suh, and J. O. McMahon, “A Voltage and Resource Synthesis Technique for Energy-Aware Real-time Systems,” The 13^th IEEE International Confereence on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007) , Daegu, Korea, August 2007 (invited).
• J. Suh, “Benchmark Implementations on MONARCH and Raw Processors,” US-Korea Conference (UKC 2007) , Herndon, VA, August 2007.
• J. Suh, R. Lethin, S. P. Crago, J. O. McMahon, and D.-I. Kang, “Evaluation of Stream Virtual Machine on Raw Processor,” High Level Parallel Programming Models and Supportive Environments, Long Beach, CA, March 2007.
• J. Suh and J. O. McMahon, “Implementations of FIR for MONARCH Processor,” High Performance Embedded Computing (HPEC), Lexington, MA, September 2006.
• J. Suh, S. P. Crago, D.-I. Kang, and J. O. McMahon, “Implementations of Signal Processing Kernels using Stream Virtual Machine for Raw Processor,” High Performance Embedded Computing (HPEC), Lexington, MA, September 2005.
• J. Cook, S. P. Crago, L. Morda, R. Pancoast, and J. Suh “Implementation of an Embedded DoD VSIPL Application on the DARPA Polymorphous Computing Architecture (PCA) Raw Processor,, High Performance Embedded Computing (HPEC), Lexington, MA, September 2005.
• S. P. Crago, M. C. French, J. Suh, C. Chen, and D. P. Campbell, Multiprocessor Performance for Polymorphous Computing Systems, Goverment Microcircuit Applications and Critical Technology Conference (GOMAC), Las Vegas, NV, April 2005.
• M. C. French, J. Suh, S. P. Crago, and J. Damoulakis, “Novel Signal Processing Architectures for Knowledge-based STAP Algorithms, IEEE Radar Conference, Philadelphia, Pensnsylvania, April 2004.
• J. Suh, D. Kang, and S. P. Crago, “Dynamic Power Management of Heterogeneous Systems,Eleventh International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS) in conjunction with IPDPS, Nice, France, April 2003.
• J. Suh, E.-G. Kim, S. P. Crago, L. Srinivasan, and M. C. French, “ A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels, ISCA03, San Diego, CA, June 2003.
• J. Suh, E.-G. Kim, S. P. Crago, L. Srinivasan, and M. C. French, “ A Performance Characterization of New Mircorprocessor paradigm on Data-Intensive Kernels , Workshop on Performance Characterization, Modeling, and Benchmarking for HPC Systems, Emeryville, CA, May 2003.
• P. M. Shriver, M. B. Gokhale, S. D. Briles, D.-I. Kang, M. Cai, K. McCabe, S. P. Crago, J. Suh, A Power-Aware, Satellite-Based Parallel Signal Processing Scheme, Power Aware Computing, Series in Computer Science, Kluwer Academic/Plenum Publishers, New York, NY, 2002.
• S. Shank, S. Crago, R. Pancoast, J. Racosky, J. Suh, L. Trevito, DARPA Data Intensive Systems (DIS) Embedded Computing Benchmarks for Critical Defense Signal Processing Applications, 6^th Annual High Performance Embedded Computing Workshop, Cambridge, MA, September 2002. (Outstanding Paper)
• D. Kang, J. Suh, and S. P. Crago, “An Optimal Voltage Synthesis Technique for a Power-Efficient Satellite Application, 39^th Design Automation Conference (DAC), New Orleans, LA, June 2002.
• J. Suh and V. K. Prasanna, “An Efficient Algorithm for Out-of-Core Matrix Transposition,” IEEE Transactions on Computer, April 2002.
• J. Suh, D. Kang, and S. P. Crago, “Dynamic Power Management of Multiprocessor Systems,” Tenth International Workshop on Parallel and Distributed Real-Time Systems (WPDRTS) in conjunction with IPDPS, Fort Lauderdale, FL, April 2002.
• J. Suh and S. P. Crago, “ PIM- and Stream Processor-based Processing for Radar Signal Applications,” The Third Workshop on Media and Streaming Processors in conjunction with The 34^th Interantional Symposium on Microarchitecture, Austin, TX, December 2001.
• J. Suh, S. P. Crago, C. Li, and R. Parker, “PIM- and Stream Processor-Based System,” Fifth Annual High Performance Embedded Computing Workshop, Cambridge, MA, November 2001.
• J Suh, D. Kang, and S. P. Crago, " Efficient Algorithms for Fixed-Point Arithmetic Operations In An Embedded PIM," SCI 01, Orlando, FL, July 2001. (A typo in division algorithm was corrected; I’d appreciate if you let me know if the new one works (or not) for your project.)
• D. Kang, S. Crago, and J. Suh, “Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems,” ACM Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES) '01, UT, Jun. 2001.
• J. Suh, C. Li, S. P. Crago, and R. Parker, "A PIM-Based Multiprocessor," IPDPS 01, San Francisco, CA, April 2001.
• J. Suh, M. Zhu, C. Li, S. P. Crago, S. F. Shank, R. H. Chau, W. J. Mazur², and R. Pancoast, " Implementations of Real-time Data Intensive Applications on PIM-based Multiprocessor Systems," Joint WPDRTS and EHPC 01, San Francisco, CA, April 2001.
• J. Suh, S. P. Crago, C. Li, and R. Parker, "Distributed Corner Turn on a PIM-Based Multiprocessor," Fourth Annual Workshop on High Performance Embedded Computing (HPEC), Cambridge, MA, September 2000.
• J. Suh and V. K. Prasanna, "An Efficient Algorithm for Large-Scale Matrix Transposition," 2000 International Conference on Parallel Processing (ICPP), Toronto, Canada, August 2000.
• J. Suh, D. Kang, and S. P. Crago, "Efficient Communication Algorithm for Multiple FPGA Systems," IEEE Symposium on Field Programmable Custom Computing Machines (FCCM) 2000, Napa, CA, April 2000.
• J. Suh and V. K. Prasanna, "Portable Implementation of Real Time Signal Processing Benchmarks on HPC Platforms," International Workshop on Applied Parallel Computing in Large Scale Scientific and Industrial Problems '98, Umea, Sweden, June 1998.
• H. Park, J. Suh, V. K. Prasanna, and M. Ung, "Parallel Implementation of 2D FFT on High Performance Computing Platforms," DoD HPC User's Conference '98, Houston, Texas, June 1998.
• J. Suh and V. K. Prasanna, "Portable Implementation of Real Time Signal Processing Benchmarks on HPC Platforms," USC Technical Report, CENG 97-18, 1997.
• J. Suh, M. Ung, and V. K. Prasanna, "Parallel Implementation of Synthetic Aperture Radar on High Performance Computing Platforms," The IEEE International Conference on Algorithms And Architectures for Parallel Processing, Melbourne, Australia, December 1997.
• J. Suh and V. K. Prasanna, "Portable Communication Algorithms for Implementing SAR," First Annual High-Performance Embedded Computing Workshop, Lexington, MA, September 1997.
• J. Suh and V. K. Prasanna, "Scalable and Portable Implementations of Real-time FFT Benchmarks," Supercomputing Conference, November 1996.
• J. Suh and S. D. Kim, “Line Detection Algorithm using A* Algorithm,” KEEE Conference, Seoul, Korea, 1989.

Inventions

- Title: A 3-branch encoder for the transmission of high-definition TV signals

Countries: England, German, France, and Netherlands

- Many other domestic (Korea) inventions.