HiDISC - Hierarchical Decoupled Instruction Stream Computer

HiDISC is a hierarchical decoupled instruction stream computer that has a compute processor, an access processer (which feeds operands from the cache to the compute processor), and a cache management processor (which can prefetch data from memory into the cache). HiDISC is designed to address the problem of increasing memory latency while taking advantage of instruction-level parallelism.

• Technical Reports/Presentations
• A Java interface to the HiDISC simulator
• The HiDISC simulator man page
• The run_dsim man page
• Compiling for the HiDISC Simulator
• Benchmarks

See also:

• Advanced Computer Architecture Laboratory
• Information Sciences Institute (ISI)
• University of Southern California

The HiDISC project receives funding from Rockwell Semiconductor Systems and DARPA.