Program Overview

The Power Aware Multiprocessor Architecture (PAMA) is a multiprocessor architecture that provides several critical mechanisms to the application programmers and design tools for efficient power management. PAMA provides support by applying known device-level power-management techniques to individual components of a multiprocessor system. PAMA allows power consumption to be varied by allowing processors to have individually-programmed clock speeds and to be put to sleep.  PAMA also allows interconnect power to be managed by varying the network implementation at run-time. PAMA supports power management in the memory system, providing full control over local, remote, and shared memory accesses. Finally, PAMA facilitates power management by providing diverse processing elements, with different performance, power-consumption, and programmability characteristics. 

The Figure below shows an overview of the PAMA system. The PAMA board provides the ability to control the power consumption of its components as described below. The Power Control Library provides a software interface for controlling the power consumption, shielding the user from the low-level hardware implementation. The interface of the Power Control Library is available to both the application programmer and synthesis tools.  The Power Aware Parameter Synthesizer will be used to automatically choose power-management parameters.

Click here to see the PAMA quad chart.  

The PAMA project is a team effort with Los Alamos National Labs, and is led by USC/ISI.  It is funded by the PACC program of the Darpa Information Technology Office

This effort is sponsored by Defense Advanced Research Projects Agency (DARPA) through the Air Force Research Laboratory, USAF, under agreement number F30602-00-2-0548.

This page was created and maintained in part by Michelle Lee, an intern during the summer of 2001.